Important step forward in microchip design research in Vietnam

The National Office of Intellectual Property (NOIP) has just granted a Patent for the invention named: "Process of assessing the security level of hardware based on estimated power consumption traces" by the Research Group of the Center for Microchip Design Research and Applications, Institute of Information Technology, Vietnam National University, Hanoi.

Intelligent Integrated Systems Research Group (SISLAB) – Center for Microchip Design Research and Applications, Institute of Information Technology, Vietnam National University, Hanoi .

This is the result of research by the Intelligent Integrated Systems Research Group (SISLAB) - Center for Microchip Design and Application Research, Institute of Information Technology, Vietnam National University, Hanoi. The work opens up an effective approach to testing the security level of microchip designs right from the design stage, before production.

Breakthrough solution in hardware security assessment

The invention provides a systematic technical process that allows the security of crypto-hardware designs to be assessed, during the design phase, through the analysis of power consumption traces estimated by simulation, instead of waiting until actual chip manufacturing.

Traditionally, hardware security testing is only performed after the design has been fabricated into an ASIC or FPGA chip, which is costly and time-consuming. With side-channel attacks becoming increasingly sophisticated, early detection of information leaks is becoming urgent.

The patented process includes steps from design specification, RTL architecture description, functional simulation, hardware synthesis, timing and parasitic analysis, to power consumption estimation and security analysis through statistical techniques such as T-test, differential approximation (DPA) and correlation analysis (CPA). The entire process is performed on the design model before sending it to manufacturing, resulting in significant cost savings and early detection of exploitable security weaknesses.

Practical applications in the design of high-security microcircuits

The invention is particularly useful in designing and evaluating hardware encryption blocks such as AES (advanced encryption standard), RSA (public key cryptography), ECC (curve-based cryptography)... serving applications requiring high security such as bank cards, electronic citizen identification, military systems, secure IoT and secure embedded devices.

For example, power-trace-based attacks can crack an AES key in minutes if the hardware design is not properly protected. This patented solution provides a powerful technical tool to verify and improve the leak-proofness of secret keys in designs.

The granting of a Patent for this solution affirms the research and development capacity of Vietnamese scientists in the field of semiconductor design and information security - a high-tech field that is being prioritized for investment and development by the Government.

This is also a testament to the effective combination of current key research directions such as hardware cryptography, side-channel security analysis, digital circuit design (RTL/ASIC/FPGA) and pre-production security design testing.

Patented technical process

The process of hardware security assessment based on power consumption estimation traces is performed through the following steps: (i) developing cryptographic/security design specifications; (ii) designing hardware in register-shifted form (RTL); (iii) simulating and verifying the design's functionality; (iv) synthesizing and implementing the design hardware; (v) extracting parasitic impedance and capacitance information, analyzing static timing to check the design's timing response; (vi) simulating the design with parasitic information and extracting signal waveforms; (vii) estimating power consumption and extracting corresponding traces; (viii) interpolating and extracting power consumption traces; (ix) security assessment based on collected traces; (x) integrating the design into the system, ready for IC fabrication.

Patent Title: Hardware Security Assessment Process Based on Power Consumption Estimation Traces
Field: Semiconductor design, hardware security
Granting authority: Department of Intellectual Property – Ministry of Science and Technology
Application: Security testing of cryptographic chip designs on ASIC/FPGA platforms before production
Research unit: Center for Microchip Design and Application Research (CICA), Institute of Information Technology, Vietnam National University, Hanoi
Inventors: Dr. Bui Duy Hieu, Professor, Dr. Tran Xuan Tu

VU QUYNH

Source: https://nhandan.vn/buoc-tien-quan-trong-trong-nghien-cuu-thiet-ke-vi-mach-tai-viet-nam-post894360.html