Keysight advances end-to-end chip verification technology

The final step in the chip design process, known as silicon tapeout, is rigorous, expensive, and leaves little room for design error. If a design fails after tapeout, chipmakers must start a new “re-spin” cycle that can last 12 months or more. The delay caused by this redesign not only requires additional, expensive research and development resources, but can also prevent chipmakers from getting their products to market on time.

Keysight Technologies offers a wide range of measurement and test solutions.

The Keysight USPA platform provides chip designers and engineers with a digital twin of complete signals to verify designs before moving to chip manufacturing, minimizing the risk of design errors and redesign costs. The USPA platform integrates ultra-fast signal converters with a high-performance FPGA prototyping system, providing designers with an alternative to proprietary, custom prototyping systems.

In addition, the solution also provides suitable input/output interfaces for applications including 6G radio application development, digital radio frequency memory, advanced physics research, and high-speed data acquisition applications, such as radar and radio astronomy.

"Keysight's USPA platform accelerates and de-risks chip development, providing a novel solution that addresses the challenges of leading-edge designs in high-cost environments," said Dr. Joachim Peerlings, vice president and general manager of Keysight's Network and Data Center Solutions Group. "This powerful platform provides chip developers with a digital twin of their future silicon device, allowing them to fully validate designs and algorithms, minimizing the risks and costs associated with redesigns."

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